Struct Uart 

pub struct Uart<'d, M: PeriMode> { /* private fields */ }

Bidirectional UART Driver, which acts as a combination of UartTx and UartRx.

Notes on embedded_io::Read

embedded_io::Read requires guarantees that the base UartRx cannot provide.

See UartRx for more details, and see BufferedUart and RingBufferedUartRx as alternatives that do provide the necessary guarantees for embedded_io::Read.

Implementations

impl<'d> Uart<'d, Async>

pub fn new<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional UART

pub fn new_with_rtscts<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional UART with request-to-send and clear-to-send pins

pub fn new_with_de<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, de: Peri<'d, impl DePin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional UART with a driver-enable pin

pub fn new_half_duplex<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, readback: HalfDuplexReadback, ) -> Result<Self, ConfigError>

Create a single-wire half-duplex Uart transceiver on a single Tx pin.

See new_half_duplex_on_rx if you would prefer to use an Rx pin (when it is available for your chip). There is no functional difference between these methods, as both allow bidirectional communication.

The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter).

pub fn new_half_duplex_on_rx<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, readback: HalfDuplexReadback, ) -> Result<Self, ConfigError>

Create a single-wire half-duplex Uart transceiver on a single Rx pin.

See new_half_duplex if you would prefer to use an Tx pin. There is no functional difference between these methods, as both allow bidirectional communication.

The pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter).

pub fn new_master<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART in synchronous master mode

pub fn new_master_with_rtscts<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with request-to-send and clear-to-send pins in synchronous master mode

pub fn new_master_with_de<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, de: Peri<'d, impl DePin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with a driver-enable pin in synchronous master mode

pub fn new_slave<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART in synchronous slave mode

pub fn new_slave_with_rtscts<T: Instance, D1: TxDma<T>, D2: RxDma<T>>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, tx_dma: Peri<'d, D1>, rx_dma: Peri<'d, D2>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D1::Interrupt, InterruptHandler<D1>> + Binding<D2::Interrupt, InterruptHandler<D2>> + 'd, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with request-to-send and clear-to-send pins in synchronous slave mode

pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error>

Perform an asynchronous write

pub async fn flush(&mut self) -> Result<(), Error>

Wait until transmission complete

pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error>

Perform an asynchronous read into buffer

pub async fn read_until_idle( &mut self, buffer: &mut [u8], ) -> Result<usize, Error>

Perform an an asynchronous read with idle line detection enabled.

WARNING: In synchronous mode, idle detection does not work, and this behaves as if you had called read(buffer) instead!

impl<'d> Uart<'d, Blocking>

pub fn new_blocking<T: Instance>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new blocking bidirectional UART.

pub fn new_blocking_with_rtscts<T: Instance>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional UART with request-to-send and clear-to-send pins

pub fn new_blocking_with_de<T: Instance>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, de: Peri<'d, impl DePin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional UART with a driver-enable pin

pub fn new_blocking_half_duplex<T: Instance>( peri: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config, readback: HalfDuplexReadback, ) -> Result<Self, ConfigError>

Create a single-wire half-duplex Uart transceiver on a single Tx pin.

See new_half_duplex_on_rx if you would prefer to use an Rx pin (when it is available for your chip). There is no functional difference between these methods, as both allow bidirectional communication.

The pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter).

pub fn new_blocking_half_duplex_on_rx<T: Instance>( peri: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config, readback: HalfDuplexReadback, ) -> Result<Self, ConfigError>

Create a single-wire half-duplex Uart transceiver on a single Rx pin.

See new_half_duplex if you would prefer to use an Tx pin. There is no functional difference between these methods, as both allow bidirectional communication.

The pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter).

pub fn new_blocking_master<T: Instance>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new blocking bidirectional USART in synchronous master mode

pub fn new_blocking_master_with_rtscts<T: Instance>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with request-to-send and clear-to-send pins in synchronous master mode

pub fn new_blocking_master_with_de<T: Instance>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, de: Peri<'d, impl DePin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with a driver-enable pin in synchronous master mode

pub fn new_blocking_slave<T: Instance>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new blocking bidirectional USART in synchronous slave mode

pub fn new_blocking_slave_with_rtscts<T: Instance>( peri: Peri<'d, T>, ck: Peri<'d, impl CkPin<T>>, rx: Peri<'d, impl RxPin<T>>, tx: Peri<'d, impl TxPin<T>>, rts: Peri<'d, impl RtsPin<T>>, cts: Peri<'d, impl CtsPin<T>>, config: Config, ) -> Result<Self, ConfigError>

Create a new bidirectional USART with request-to-send and clear-to-send pins in synchronous slave mode

impl<'d, M: PeriMode> Uart<'d, M>

pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error>

Perform a blocking write

pub fn blocking_flush(&mut self) -> Result<(), Error>

Block until transmission complete

pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error>

Perform a blocking read into buffer

pub fn split(self) -> (UartTx<'d, M>, UartRx<'d, M>)

Split the Uart into a transmitter and receiver, which is particularly useful when having two tasks correlating to transmitting and receiving.

pub fn split_ref(&mut self) -> (&mut UartTx<'d, M>, &mut UartRx<'d, M>)

Split the Uart into a transmitter and receiver by mutable reference, which is particularly useful when having two tasks correlating to transmitting and receiving.

pub fn send_break(&self)

Send break character

pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError>

Set baudrate

Trait Implementations

impl<'d, M: PeriMode> ErrorType for Uart<'d, M>

type Error = Error

Error type

impl<M: PeriMode> ErrorType for Uart<'_, M>

type Error = Error

Error type of all the IO operations on this type.

impl<'d, M: PeriMode> Read for Uart<'d, M>

fn read(&mut self) -> Result<u8, Error<Self::Error>>

Reads a single word from the serial interface

impl<'d, M: PeriMode> Read<u8> for Uart<'d, M>

type Error = Error

Read error

fn read(&mut self) -> Result<u8, Error<Self::Error>>

Reads a single word from the serial interface

impl<'d, M: PeriMode> SetConfig for Uart<'d, M>

type Config = Config

The configuration type used by this driver.

type ConfigError = ConfigError

The error type that can occur if set_config fails.

fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError>

Set the configuration of the driver.

impl<'d, M: PeriMode> Write for Uart<'d, M>

fn write(&mut self, char: u8) -> Result<(), Self::Error>

Writes a single word to the serial interface.

fn flush(&mut self) -> Result<(), Self::Error>

Ensures that none of the previously written words are still buffered.

impl<M: PeriMode> Write for Uart<'_, M>

fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error>

Write a buffer into this writer, returning how many bytes were written.

fn flush(&mut self) -> Result<(), Self::Error>

Flush this output stream, blocking until all intermediately buffered contents reach their destination.

fn write_all(&mut self, buf: &[u8]) -> Result<(), Self::Error>

Write an entire buffer into this writer.

fn write_fmt( &mut self, fmt: Arguments<'_>, ) -> Result<(), WriteFmtError<Self::Error>>

Write a formatted string into this writer, returning any error encountered.

impl Write for Uart<'_, Async>

async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error>

Write a buffer into this writer, returning how many bytes were written.

async fn flush(&mut self) -> Result<(), Self::Error>

Flush this output stream, ensuring that all intermediately buffered contents reach their destination.

async fn write_all(&mut self, buf: &[u8]) -> Result<(), Self::Error>

Write an entire buffer into this writer.

impl<'d, M: PeriMode> Write<u8> for Uart<'d, M>

type Error = Error

The type of error that can occur when writing

fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error>

Writes a slice, blocking until everything has been written

fn bflush(&mut self) -> Result<(), Self::Error>

Block until the serial interface has sent all buffered words