Struct Sdmmc 

pub struct Sdmmc<'d> { /* private fields */ }

Sdmmc device

Implementations

impl<'d> Sdmmc<'d>

pub fn new_1bit<T: Instance, D: SdmmcDma<T>>( sdmmc: Peri<'d, T>, dma: Peri<'d, D>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D::Interrupt, InterruptHandler<D>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 1 data lane.

pub fn new_4bit<T: Instance, D: SdmmcDma<T>>( sdmmc: Peri<'d, T>, dma: Peri<'d, D>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D::Interrupt, InterruptHandler<D>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 4 data lanes.

impl<'d> Sdmmc<'d>

pub fn new_8bit<T: Instance, D: SdmmcDma<T>>( sdmmc: Peri<'d, T>, dma: Peri<'d, D>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + Binding<D::Interrupt, InterruptHandler<D>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 8 data lanes.

Trait Implementations

impl<'d> Drop for Sdmmc<'d>

fn drop(&mut self)

Executes the destructor for this type.

impl<'d> MmcBus for Sdmmc<'d>

fn supports_1v8(&self) -> bool

Optional: whether the host supports 1.8v. If true, send_command will be called with CMD11.

fn supports_bus_width(&self) -> BusWidth

Optional: the maximum bus width available to the host

fn supports_frequency(&self) -> u32

Optional: the maximum frequency supported by this bus. Defaults to 25Mhz

fn supports_mmc(&self) -> bool

Optional: whether the host supports native MMC mode. Otherwise, SPI mode is used.

async fn init_idle(&mut self, hz: u32) -> Result<(), MmcError>

Initialize the bus in one-bit mode at 3.3v and the requested frequency.

async fn tune_bus<O>( &mut self, width: BusWidth, hz: u32, _op: &mut O, ) -> Result<(), MmcError>

where O: TuningOp,

Tune the bus, if required. Called after the bus is set to the target frequency; needed for uhs.

fn set_bus(&mut self, width: BusWidth, hz: u32) -> Result<(), MmcError>

Configure bus width and frequency.

async fn send_command<'a, C>(&mut self, cmd: C) -> Result<C::Resp<'a>, MmcError>

where C: ControlCommand + 'a,

Send a command that has no data transfer (e.g., CMD0, CMD8, CMD55).

async fn read_blocks<'a, C>(&mut self, cmd: C) -> Result<C::Resp<'a>, MmcError>

where C: BlockReadCommand + 'a,

Read N blocks of fixed size (CMD17, CMD18, CMD53 block mode).

async fn write_blocks<'a, C>(&mut self, cmd: C) -> Result<C::Resp<'a>, MmcError>

where C: BlockWriteCommand + 'a,

Write N blocks of fixed size (CMD24, CMD25, CMD53 block mode).

async fn read_bytes<'a, C>(&mut self, cmd: C) -> Result<C::Resp<'a>, MmcError>

where C: ByteReadCommand + 'a,

Read an arbitrary number of bytes (CMD53 byte mode, SPI multi-byte).

async fn write_bytes<'a, C>(&mut self, cmd: C) -> Result<C::Resp<'a>, MmcError>

where C: ByteWriteCommand + 'a,

Write an arbitrary number of bytes (CMD53 byte mode, SPI multi-byte).