Struct Dfsdm 

pub struct Dfsdm<'d, T: Instance, C: ClockOutputMode> { /* private fields */ }

DFSDM driver entry point.

Implementations

impl<'d, T> Dfsdm<'d, T, OutputEnabled>

where T: Instance,

pub fn new_ckout( peri: Peri<'d, T>, ckout: Peri<'d, impl CkoutPin<T>>, ckout_source: CkoutSource, ckout_div: CkoutDivider, ) -> Self

Create the driver with an output clock on ckout.

impl<'d, T> Dfsdm<'d, T, OutputDisabled>

where T: Instance,

pub fn new(peri: Peri<'d, T>) -> Self

Create the driver without an output clock.

impl<'d, T, C> Dfsdm<'d, T, C>

where T: Instance + HasHwid, C: ClockOutputMode,

pub fn hwid() -> Hwid

Reads the DFSDM version/ID register cluster (HWCFGR, VERR, IPIDR, SIDR).

filter_count/transceiver_count self-describe the silicon; embassy’s compile-time capability tags remain the primary shape mechanism. This is informational, not a runtime capability probe.

impl<'d, T, C> Dfsdm<'d, T, C>

where T: Instance, C: ClockOutputMode,

pub fn configure_pins<F, OUT>( self, f: F, ) -> (DfsdmCommon<'d, T, Enabled>, <OUT as ChannelCfgTuple<'d, T, C>>::Split)

where F: FnOnce(<T::Transceivers as Shape>::Selectors<T>) -> OUT, OUT: ChannelCfgTuple<'d, T, C>,

The closure receives one selector per transceiver the instance actually has, and must return one token per transceiver, as a tuple in the same order.

// DFSDM instance with 8-transceiver capability:

dfsdm1.configure_pins(|tb| {
    (
        tb.ch0.datin_ckin(p.PC1, p.PC0),
        tb.ch1.datin(p.PC3),
        tb.ch2.datin_ckin(p.PC5, p.PC4),
        tb.ch3.none(),
        tb.ch4.none(),
        tb.ch5.none(),
        tb.ch6.none(),
        tb.ch7.none(),
    )
});

// DFSDM instance with 2-transceiver capability:

dfsdm1.configure_pins(|tb| {
    (
        tb.ch0.datin_ckin(p.PC1, p.PC0),
        tb.ch1.datin(p.PC3),
    )
});