Struct Transceiver 

pub struct Transceiver<'a, 'd, T, M, S, MODE, PS, P>
where
    T: Instance,
    M: TransceiverMarker + NextChannelForInstance<T>,
    S: PinSet,
    MODE: ChannelMode,
    PS: PinSource,
    P: PowerState,
{ /* private fields */ }

Configured DFSDM data input transceiver.

Implementations

impl<'a, 'd, T, M, S, MODE, PS> Transceiver<'a, 'd, T, M, S, MODE, PS, Enabled>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode, PS: PinSource,

Only when enabled

pub fn disable(self) -> Transceiver<'a, 'd, T, M, S, MODE, PS, Disabled>

Disables the transceiver.

pub fn set_offset(&mut self, offset: u32)

Set the transceiver’s offset.

impl<'a, 'd, T, M, S, MODE, PS> Transceiver<'a, 'd, T, M, S, MODE, PS, Enabled>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode + ExternalSerialMode, PS: PinSource,

pub async fn wait_for_sync(&mut self)

Wait until this transceiver’s clock-absence flag clears, indicating it is synchronized. Only meaningful for externally-clocked serial modes.

impl<'a, 'd, T, M, S, MODE, PS> Transceiver<'a, 'd, T, M, S, MODE, PS, Disabled>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode, PS: PinSource,

Only when disabled

pub fn enable(self) -> Transceiver<'a, 'd, T, M, S, MODE, PS, Enabled>

Enables the transceiver.

pub fn set_data_right_shift(self, shift: DataRightShift) -> Self

Set the transceiver’s right-shift factor.

pub fn select_awd_filter_order(self, filter_order: AwdFilterOrder) -> Self

Set the analog watchdog filter’s order.

Note

The valid watchdog OSR range depends on this order; set select_awd_filter_osr accordingly.

pub fn select_awd_filter_osr(self, osr: AwdFilterOsr) -> Self

Set the analog watchdog filter’s OSR.

Note

The valid OSR range depends on the order set via select_awd_filter_order.

pub fn set_offset(self, offset: u32) -> Self

Set the transceiver’s offset.

impl<'a, 'd, T, M, S, PS, P> Transceiver<'a, 'd, T, M, S, ParallelStandard, PS, P>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, P: PowerState, PS: PinSource,

pub fn get_datinr_as_ptr(&self) -> *mut u32

Pointer to the DATINR register, for feeding samples via DMA.

Use this as the destination of a memory-to-peripheral transfer (e.g. crate::dma::WritableRingBuffer); one 16-bit sample per word.

pub fn write(&self, data: u16)

Write one sample into the DATINR register (Standard packing).

Loads data into INDAT0[15:0]; the upper INDAT1[15:0] field is ignored and write-protected in this mode. One 16-bit sample per write.

Note

DATINR is not buffered: a sample written before the conversion starts is lost, so data must be present when the filter latches it.

impl<'a, 'd, T, M, S, PS, P> Transceiver<'a, 'd, T, M, S, ParallelInterleaved, PS, P>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, P: PowerState, PS: PinSource,

pub fn get_datinr_as_ptr(&self) -> *mut u32

Pointer to the DATINR register, for feeding samples via DMA.

Use this as the destination of a memory-to-peripheral transfer (e.g. crate::dma::WritableRingBuffer); two 16-bit samples per word.

pub fn write(&self, data: [u16; 2])

Write two samples into the DATINR register (Interleaved packing).

Loads data[0] into INDAT0[15:0] and data[1] into INDAT1[15:0]; both are read sequentially by the same filter on channel y. Two 16-bit samples per 32-bit write.

Note

DATINR is not buffered: samples written before the conversion starts are lost, so data must be present when the filter latches it.

impl<'a, 'd, T, M, S, MODE, PS, P> Transceiver<'a, 'd, T, M, S, MODE, PS, P>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode, P: PowerState, PS: PinSource,

Any powerstate

pub fn awd_filter_data(&self) -> u16

Read the analog watchdog data for this transceiver, converted by the watchdog filter (continuously, with limited resolution).

impl<'a, 'd, T, M, S, MODE, PS, P> Transceiver<'a, 'd, T, M, S, MODE, PS, P>

where T: Instance + HasDelay, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode + SerialMode, P: PowerState, PS: PinSource,

pub fn skip_progress(&self) -> u8

Reads back pulses still to skip, 0 = done

pub fn skip_pulses(&mut self, skips: PulsesToSkip)

Configure to skip the next skips pulses (max 63 per write).

Skipping starts immediately on write; updating mid-skip is allowed. To skip more than 63 pulses, issue repeated writes; the peripheral doesn’t track a cumulative count across writes, so the caller must.

Trait Implementations

impl<'a, 'd, T, M, S, MODE, PS, P> Drop for Transceiver<'a, 'd, T, M, S, MODE, PS, P>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode, PS: PinSource, P: PowerState,

fn drop(&mut self)

Executes the destructor for this type.

fn pin_drop(self: Pin<&mut Self>)

🔬This is a nightly-only experimental API. (pin_ergonomics)

Execute the destructor for this type, but different to Drop::drop, it requires self to be pinned.

impl<'a, 'd, T, M, S, MODE, PS, P> TransceiverTrait<T, P> for Transceiver<'a, 'd, T, M, S, MODE, PS, P>

where T: Instance, M: TransceiverMarker + NextChannelForInstance<T>, S: PinSet, MODE: ChannelMode, PS: PinSource, P: PowerState,

fn index(&self) -> usize

Returns this transceiver’s channel index.