Module cache 

Cache maintenance for NPU inference.

Two caches sit between the memories and the compute:

• CACHEAXI (“NPU cache”): a write-back cache on the NPU’s AXI masters, used for weights/activations in external memory. The peripheral base is exposed by stm32-metapac (as pac::CACHEAXI, an opaque *mut ()), but its register block is not currently modelled in stm32-data — so the individual registers are still accessed here through a minimal hand-written map (offsets from RM0486 / the STM32N6 CMSIS device header). Clock and reset still go through pac::RCC.
• The Cortex-M55 data cache: when input/output buffers live in MCU-cacheable memory, the CPU cache must be cleaned before the NPU reads and invalidated before the CPU reads back results. The generated network code calls these operations LL_ATON_Cache_MCU_* — the equivalents here are mcu_clean_range / mcu_invalidate_range.

The functions mirror npu_cache.c + stm32n6xx_hal_cacheaxi.c from the ST examples.

Functions

mcu_clean_invalidate_range

Clean and invalidate the CPU data cache for [start, start + len). Equivalent of LL_ATON_Cache_MCU_Clean_Invalidate_Range.

mcu_clean_range

Clean (write back) the CPU data cache for [start, start + len). Equivalent of LL_ATON_Cache_MCU_Clean_Range. Call after the CPU writes an input buffer and before the NPU reads it.

mcu_invalidate_range

Invalidate the CPU data cache for [start, start + len). Equivalent of LL_ATON_Cache_MCU_Invalidate_Range. Call after the NPU writes an output buffer and before the CPU reads it.

npu_cache_clean_invalidate_range

Write back and invalidate an address range in the NPU cache. Equivalent of LL_ATON_Cache_NPU_Clean_Invalidate_Range.

npu_cache_clean_range

Write back (clean) an address range from the NPU cache to memory. Equivalent of LL_ATON_Cache_NPU_Clean_Range.

npu_cache_debug_state

Raw (CR1, SR) state for one-time bring-up diagnostics.

npu_cache_disable

Disable the NPU cache and gate its clock.

npu_cache_enable

Enable the NPU cache (CACHEAXI): switches on its RCC clock, pulses its reset and sets the enable bit. The parent NPU clock domain must already be enabled and released from reset (for example by super::Npu::new), matching ST’s NPU_Config() ordering. Call once before running inferences that touch cacheable memory pools (external flash / PSRAM).

npu_cache_invalidate

Invalidate the entire NPU cache. Blocks until done.

npu_cache_monitor_reset

Reset and start the CACHEAXI read hit/miss monitors.

npu_cache_read_counters

Return cumulative CACHEAXI (read_hits, read_misses) monitor values.