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embassy_stm32::interrupt

Enum Interrupt

pub enum Interrupt {

Show 127 variants    WWDG = 0,
    PVD_PVM = 1,
    RTC = 2,
    RTC_S = 3,
    TAMP = 4,
    RAMCFG = 5,
    FLASH = 6,
    FLASH_S = 7,
    GTZC = 8,
    RCC = 9,
    RCC_S = 10,
    EXTI0 = 11,
    EXTI1 = 12,
    EXTI2 = 13,
    EXTI3 = 14,
    EXTI4 = 15,
    EXTI5 = 16,
    EXTI6 = 17,
    EXTI7 = 18,
    EXTI8 = 19,
    EXTI9 = 20,
    EXTI10 = 21,
    EXTI11 = 22,
    EXTI12 = 23,
    EXTI13 = 24,
    EXTI14 = 25,
    EXTI15 = 26,
    IWDG = 27,
    GPDMA1_CHANNEL0 = 29,
    GPDMA1_CHANNEL1 = 30,
    GPDMA1_CHANNEL2 = 31,
    GPDMA1_CHANNEL3 = 32,
    GPDMA1_CHANNEL4 = 33,
    GPDMA1_CHANNEL5 = 34,
    GPDMA1_CHANNEL6 = 35,
    GPDMA1_CHANNEL7 = 36,
    ADC1_2 = 37,
    DAC1 = 38,
    FDCAN1_IT0 = 39,
    FDCAN1_IT1 = 40,
    TIM1_BRK = 41,
    TIM1_UP = 42,
    TIM1_TRG_COM = 43,
    TIM1_CC = 44,
    TIM2 = 45,
    TIM3 = 46,
    TIM4 = 47,
    TIM5 = 48,
    TIM6 = 49,
    TIM7 = 50,
    TIM8_BRK = 51,
    TIM8_UP = 52,
    TIM8_TRG_COM = 53,
    TIM8_CC = 54,
    I2C1_EV = 55,
    I2C1_ER = 56,
    I2C2_EV = 57,
    I2C2_ER = 58,
    SPI1 = 59,
    SPI2 = 60,
    USART1 = 61,
    USART2 = 62,
    USART3 = 63,
    UART4 = 64,
    UART5 = 65,
    LPUART1 = 66,
    LPTIM1 = 67,
    LPTIM2 = 68,
    TIM15 = 69,
    TIM16 = 70,
    TIM17 = 71,
    COMP = 72,
    OTG_HS = 73,
    CRS = 74,
    FMC = 75,
    OCTOSPI1 = 76,
    PWR_S3WU = 77,
    SDMMC1 = 78,
    SDMMC2 = 79,
    GPDMA1_CHANNEL8 = 80,
    GPDMA1_CHANNEL9 = 81,
    GPDMA1_CHANNEL10 = 82,
    GPDMA1_CHANNEL11 = 83,
    GPDMA1_CHANNEL12 = 84,
    GPDMA1_CHANNEL13 = 85,
    GPDMA1_CHANNEL14 = 86,
    GPDMA1_CHANNEL15 = 87,
    I2C3_EV = 88,
    I2C3_ER = 89,
    SAI1 = 90,
    SAI2 = 91,
    TSC = 92,
    RNG = 94,
    FPU = 95,
    HASH = 96,
    LPTIM3 = 98,
    SPI3 = 99,
    I2C4_ER = 100,
    I2C4_EV = 101,
    MDF1_FLT0 = 102,
    MDF1_FLT1 = 103,
    MDF1_FLT2 = 104,
    MDF1_FLT3 = 105,
    UCPD1 = 106,
    ICACHE = 107,
    LPTIM4 = 110,
    DCACHE1 = 111,
    ADF1 = 112,
    ADC4 = 113,
    LPDMA1_CHANNEL0 = 114,
    LPDMA1_CHANNEL1 = 115,
    LPDMA1_CHANNEL2 = 116,
    LPDMA1_CHANNEL3 = 117,
    DMA2D = 118,
    DCMI_PSSI = 119,
    OCTOSPI2 = 120,
    MDF1_FLT4 = 121,
    MDF1_FLT5 = 122,
    CORDIC = 123,
    FMAC = 124,
    LSECSSD = 125,
    USART6 = 126,
    I2C5_ER = 127,
    I2C5_EV = 128,
    I2C6_ER = 129,
    I2C6_EV = 130,
    HSPI1 = 131,

}

Variants§

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WWDG = 0

0 - WWDG

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PVD_PVM = 1

1 - PVD_PVM

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RTC = 2

2 - RTC

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RTC_S = 3

3 - RTC_S

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TAMP = 4

4 - TAMP

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RAMCFG = 5

5 - RAMCFG

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FLASH = 6

6 - FLASH

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FLASH_S = 7

7 - FLASH_S

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GTZC = 8

8 - GTZC

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RCC = 9

9 - RCC

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RCC_S = 10

10 - RCC_S

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EXTI0 = 11

11 - EXTI0

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EXTI1 = 12

12 - EXTI1

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EXTI2 = 13

13 - EXTI2

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EXTI3 = 14

14 - EXTI3

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EXTI4 = 15

15 - EXTI4

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EXTI5 = 16

16 - EXTI5

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EXTI6 = 17

17 - EXTI6

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EXTI7 = 18

18 - EXTI7

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EXTI8 = 19

19 - EXTI8

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EXTI9 = 20

20 - EXTI9

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EXTI10 = 21

21 - EXTI10

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EXTI11 = 22

22 - EXTI11

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EXTI12 = 23

23 - EXTI12

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EXTI13 = 24

24 - EXTI13

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EXTI14 = 25

25 - EXTI14

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EXTI15 = 26

26 - EXTI15

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IWDG = 27

27 - IWDG

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GPDMA1_CHANNEL0 = 29

29 - GPDMA1_CHANNEL0

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GPDMA1_CHANNEL1 = 30

30 - GPDMA1_CHANNEL1

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GPDMA1_CHANNEL2 = 31

31 - GPDMA1_CHANNEL2

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GPDMA1_CHANNEL3 = 32

32 - GPDMA1_CHANNEL3

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GPDMA1_CHANNEL4 = 33

33 - GPDMA1_CHANNEL4

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GPDMA1_CHANNEL5 = 34

34 - GPDMA1_CHANNEL5

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GPDMA1_CHANNEL6 = 35

35 - GPDMA1_CHANNEL6

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GPDMA1_CHANNEL7 = 36

36 - GPDMA1_CHANNEL7

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ADC1_2 = 37

37 - ADC1_2

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DAC1 = 38

38 - DAC1

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FDCAN1_IT0 = 39

39 - FDCAN1_IT0

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FDCAN1_IT1 = 40

40 - FDCAN1_IT1

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TIM1_BRK = 41

41 - TIM1_BRK

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TIM1_UP = 42

42 - TIM1_UP

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TIM1_TRG_COM = 43

43 - TIM1_TRG_COM

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TIM1_CC = 44

44 - TIM1_CC

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TIM2 = 45

45 - TIM2

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TIM3 = 46

46 - TIM3

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TIM4 = 47

47 - TIM4

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TIM5 = 48

48 - TIM5

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TIM6 = 49

49 - TIM6

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TIM7 = 50

50 - TIM7

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TIM8_BRK = 51

51 - TIM8_BRK

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TIM8_UP = 52

52 - TIM8_UP

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TIM8_TRG_COM = 53

53 - TIM8_TRG_COM

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TIM8_CC = 54

54 - TIM8_CC

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I2C1_EV = 55

55 - I2C1_EV

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I2C1_ER = 56

56 - I2C1_ER

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I2C2_EV = 57

57 - I2C2_EV

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I2C2_ER = 58

58 - I2C2_ER

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SPI1 = 59

59 - SPI1

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SPI2 = 60

60 - SPI2

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USART1 = 61

61 - USART1

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USART2 = 62

62 - USART2

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USART3 = 63

63 - USART3

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UART4 = 64

64 - UART4

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UART5 = 65

65 - UART5

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LPUART1 = 66

66 - LPUART1

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LPTIM1 = 67

67 - LPTIM1

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LPTIM2 = 68

68 - LPTIM2

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TIM15 = 69

69 - TIM15

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TIM16 = 70

70 - TIM16

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TIM17 = 71

71 - TIM17

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COMP = 72

72 - COMP

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OTG_HS = 73

73 - OTG_HS

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CRS = 74

74 - CRS

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FMC = 75

75 - FMC

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OCTOSPI1 = 76

76 - OCTOSPI1

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PWR_S3WU = 77

77 - PWR_S3WU

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SDMMC1 = 78

78 - SDMMC1

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SDMMC2 = 79

79 - SDMMC2

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GPDMA1_CHANNEL8 = 80

80 - GPDMA1_CHANNEL8

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GPDMA1_CHANNEL9 = 81

81 - GPDMA1_CHANNEL9

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GPDMA1_CHANNEL10 = 82

82 - GPDMA1_CHANNEL10

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GPDMA1_CHANNEL11 = 83

83 - GPDMA1_CHANNEL11

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GPDMA1_CHANNEL12 = 84

84 - GPDMA1_CHANNEL12

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GPDMA1_CHANNEL13 = 85

85 - GPDMA1_CHANNEL13

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GPDMA1_CHANNEL14 = 86

86 - GPDMA1_CHANNEL14

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GPDMA1_CHANNEL15 = 87

87 - GPDMA1_CHANNEL15

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I2C3_EV = 88

88 - I2C3_EV

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I2C3_ER = 89

89 - I2C3_ER

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SAI1 = 90

90 - SAI1

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SAI2 = 91

91 - SAI2

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TSC = 92

92 - TSC

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RNG = 94

94 - RNG

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FPU = 95

95 - FPU

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HASH = 96

96 - HASH

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LPTIM3 = 98

98 - LPTIM3

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SPI3 = 99

99 - SPI3

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I2C4_ER = 100

100 - I2C4_ER

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I2C4_EV = 101

101 - I2C4_EV

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MDF1_FLT0 = 102

102 - MDF1_FLT0

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MDF1_FLT1 = 103

103 - MDF1_FLT1

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MDF1_FLT2 = 104

104 - MDF1_FLT2

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MDF1_FLT3 = 105

105 - MDF1_FLT3

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UCPD1 = 106

106 - UCPD1

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ICACHE = 107

107 - ICACHE

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LPTIM4 = 110

110 - LPTIM4

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DCACHE1 = 111

111 - DCACHE1

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ADF1 = 112

112 - ADF1

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ADC4 = 113

113 - ADC4

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LPDMA1_CHANNEL0 = 114

114 - LPDMA1_CHANNEL0

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LPDMA1_CHANNEL1 = 115

115 - LPDMA1_CHANNEL1

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LPDMA1_CHANNEL2 = 116

116 - LPDMA1_CHANNEL2

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LPDMA1_CHANNEL3 = 117

117 - LPDMA1_CHANNEL3

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DMA2D = 118

118 - DMA2D

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DCMI_PSSI = 119

119 - DCMI_PSSI

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OCTOSPI2 = 120

120 - OCTOSPI2

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MDF1_FLT4 = 121

121 - MDF1_FLT4

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MDF1_FLT5 = 122

122 - MDF1_FLT5

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CORDIC = 123

123 - CORDIC

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FMAC = 124

124 - FMAC

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LSECSSD = 125

125 - LSECSSD

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USART6 = 126

126 - USART6

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I2C5_ER = 127

127 - I2C5_ER

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I2C5_EV = 128

128 - I2C5_EV

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I2C6_ER = 129

129 - I2C6_ER

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I2C6_EV = 130

130 - I2C6_EV

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HSPI1 = 131

131 - HSPI1

Trait Implementations§

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impl Clone for Interrupt

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fn clone(&self) -> Interrupt

Returns a copy of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for Interrupt

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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more
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impl InterruptNumber for Interrupt

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fn number(self) -> u16

Return the interrupt number associated with this variant. Read more
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impl PartialEq for Interrupt

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fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl Copy for Interrupt

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impl Eq for Interrupt

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impl StructuralPartialEq for Interrupt

Auto Trait Implementations§

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T> InterruptExt for T
where T: InterruptNumber + Copy,

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unsafe fn enable(self)

Enable the interrupt.
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fn disable(self)

Disable the interrupt.
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fn is_active(self) -> bool

Check if interrupt is being handled.
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fn is_enabled(self) -> bool

Check if interrupt is enabled.
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fn is_pending(self) -> bool

Check if interrupt is pending.
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fn pend(self)

Set interrupt pending.
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fn unpend(self)

Unset interrupt pending.
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fn get_priority(self) -> Priority

Get the priority of the interrupt.
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fn set_priority(self, prio: Priority)

Set the interrupt priority.
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fn set_priority_with_cs(self, _cs: CriticalSection<'_>, prio: Priority)

Set the interrupt priority with an already-acquired critical section Read more
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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.