Struct TenbasetPhy 

pub struct TenbasetPhy { /* private fields */ }

MCX-A5 10BASE-T1S digital PHY at 0x4002d000 (XML T1S0; metadata _10BASE_T1S0). All registers and fieldset storage are 16-bit. No analog PMD, driver or protocol state machine is implemented here. Fixed 10 Mbit/s half duplex. Read-only subfields are documented, not enforced within writable fieldsets. PHYSTAT is clear-on-read; interrupt capture and diagnostic flags are write-one-to-clear. PLCADIAG3/4 counters clear by writing all zeros, not ones. Interrupt enable set/clear registers are aliases. PCSDIAG1/2 and PLCARECST are ordinary read-only values: chapter 54 does not specify read-clear behavior. Numeric fields are raw to preserve legal ranges and reserved holes; do not treat multibit values as booleans. reset_value supplies software Default from the manual reset tables, not observed hardware; live flags can change after reset release.

Implementations

impl TenbasetPhy

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn phyctrl(self) -> Reg<Phyctrl, RW>

PHY control. RESET is the soft-reset command (the manual says write clears bits). SPD1/SPD0 and DUPLX are fixed read-only indicators (10 Mbit/s, half duplex).

pub const fn phystat(self) -> Reg<Phystat, R>

PHY status. LJAB and RJAB are clear-on-read; reads are destructive.

pub const fn phyid0(self) -> Reg<Phyid0, R>

PHY Identifier0.

pub const fn phyid1(self) -> Reg<Phyid1, R>

PHY Identifier1.

pub const fn base1ext(self) -> Reg<Base1Ext, R>

PHY BASE-T1 Extended.

pub const fn pmapmdctrl(self) -> Reg<Pmapmdctrl, R>

PMA/PMD Control.

pub const fn pmactrl(self) -> Reg<Pmactrl, RW>

PMA CTRL.

pub const fn pmastat(self) -> Reg<Pmastat, R>

PMA Status.

pub const fn pmatm(self) -> Reg<Pmatm, RW>

PMA Test Mode.

pub const fn pcsctrl(self) -> Reg<Pcsctrl, RW>

PCS Control.

pub const fn pcsstat(self) -> Reg<Pcsstat, R>

PCS Status.

pub const fn pcsdiag1(self) -> Reg<Pcsdiag1, R>

PCS Remote Jabber Counter.

pub const fn pcsdiag2(self) -> Reg<Pcsdiag2, R>

PCS Physical Collisions Counter.

pub const fn plcaidver(self) -> Reg<Plcaidver, R>

PLCA Identification and Version.

pub const fn plcactrl0(self) -> Reg<Plcactrl0, RW>

PLCA Control0.

pub const fn plcactrl1(self) -> Reg<Plcactrl1, RW>

PLCA Control1.

pub const fn plcastat(self) -> Reg<Plcastat, R>

PLCA Status.

pub const fn plcatotmr(self) -> Reg<Plcatotmr, RW>

PLCA Transmit Opportunity Timer.

pub const fn plcaburst(self) -> Reg<Plcaburst, RW>

PLCA Burst Mode Configuration.

pub const fn plcarecst(self) -> Reg<Plcarecst, R>

PLCA Status.

pub const fn modectrl(self) -> Reg<Modectrl, RW>

MODE Control.

pub const fn modecfg(self) -> Reg<Modecfg, RW>

Mode Configuration.

pub const fn modestat(self) -> Reg<Modestat, R>

Mode Status.

pub const fn wkctrl(self) -> Reg<Wkctrl, RW>

Wake Control.

pub const fn wkcfg(self) -> Reg<Wkcfg, RW>

Wake Configuration.

pub const fn wupctrl(self) -> Reg<Wupctrl, RW>

Wake Control.

pub const fn wupcfg(self) -> Reg<Wupcfg, RW>

Wakeup Configuration.

pub const fn wupstat(self) -> Reg<Wupstat, R>

Wakeup Status.

pub const fn smidata(self) -> Reg<Smidata, RW>

SMI Frame DATA.

pub const fn smictrl(self) -> Reg<Smictrl, RW>

SMI Control. In TXCCFG mode, every write to SMICTRL triggers an SMI transaction. Check SMISTAT[READY] before starting an access. For write transactions, stage SMIDATA first. Prepare the complete control word (ST, OP, PA, RA and TA) before issuing one register write; separate field writes can trigger unintended intermediate transactions. See section 54.4.2, manual lines 171146-171160.

pub const fn smicfg(self) -> Reg<Smicfg, RW>

SMI Configuration.

pub const fn smistat(self) -> Reg<Smistat, R>

SMI Status.

pub const fn intencapt1(self) -> Reg<Intencapt1, RW>

Interrupt Capture1. Captured interrupt flags are write-one-to-clear; write only intended acknowledgement bits.

pub const fn intenset1(self) -> Reg<Intenset1, RW>

Interrupt Enable Set1. Set alias for interrupt enable state: writing one enables the corresponding interrupt; zero has no effect.

pub const fn intenclr1(self) -> Reg<Intenclr1, RW>

Interrupt Enable Clear1. Clear alias for interrupt enable state: writing one disables the corresponding interrupt; zero has no effect.

pub const fn intstat1(self) -> Reg<Intstat1, R>

Interrupt Status1.

pub const fn intencapt2(self) -> Reg<Intencapt2, RW>

Interrupt Capture2. Captured interrupt flags are write-one-to-clear; write only intended acknowledgement bits.

pub const fn intenset2(self) -> Reg<Intenset2, RW>

Interrupt Enable Set1. Set alias for interrupt enable state: writing one enables the corresponding interrupt; zero has no effect.

pub const fn intenclr2(self) -> Reg<Intenclr2, RW>

Interrupt Enable Clear2. Clear alias for interrupt enable state: writing one disables the corresponding interrupt; zero has no effect.

pub const fn intstat2(self) -> Reg<Intstat2, R>

Interrupt Status2.

pub const fn plcadiag1(self) -> Reg<Plcadiag1, RW>

PLCA TC14 Adv diagnostics. Diagnostic flags are write-one-to-clear.

pub const fn plcadiag2(self) -> Reg<Plcadiag2, RW>

PLCA NXP prop diagnostics. Diagnostic flags are write-one-to-clear.

pub const fn plcadiag3(self) -> Reg<Plcadiag3, RW>

PLCA Beacon Counter Diagnostics. Write all zeros to clear the receive-beacon counter; this is not write-one-to-clear.

pub const fn plcadiag4(self) -> Reg<Plcadiag4, RW>

PLCA TO Counter Diagnostics. Write all zeros to clear the transmit-opportunity counter; this is not write-one-to-clear.

pub const fn txcdiag(self) -> Reg<Txcdiag, RW>

Transceiver Diagnostics. Diagnostic flags are write-one-to-clear; live flags can change after reset release.

pub const fn mskplcadiag1(self) -> Reg<Mskplcadiag1, RW>

Mask Control PLCADIAG1 Flag.

pub const fn mskplcadiag2(self) -> Reg<Mskplcadiag2, RW>

Mask Control PLCADIAG2 Flags.

pub const fn msktxcdiag(self) -> Reg<Msktxcdiag, RW>

Mask Control TXCDIAG Flag.

pub const fn accessctrl(self) -> Reg<Accessctrl, RW>

Global Access Control. ACCESS gates APB writes to the static registers listed in section 54.5.1; this is a PHY configuration gate, not security provisioning.

pub const fn dbgctrl(self) -> Reg<Dbgctrl, RW>

Debug Control.

pub const fn version(self) -> Reg<Version, R>

Version Information.

Trait Implementations

impl Clone for TenbasetPhy

fn clone(&self) -> TenbasetPhy

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for TenbasetPhy

fn eq(&self, other: &TenbasetPhy) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for TenbasetPhy

impl Eq for TenbasetPhy

impl Send for TenbasetPhy

impl StructuralPartialEq for TenbasetPhy

impl Sync for TenbasetPhy