Struct stm32_metapac::rcc::regs::Pllsscgr

#[repr(transparent)]
pub struct Pllsscgr(pub u32);

RCC PLL1 Spread Spectrum Clock Generator register.

Tuple Fields

0: u32

Implementations

impl Pllsscgr

pub const fn mod_per(&self) -> u16

Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.

pub fn set_mod_per(&mut self, val: u16)

Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.

pub const fn tpdfn_dis1(&self) -> bool

Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.

pub fn set_tpdfn_dis1(&mut self, val: bool)

Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.

pub const fn rpdfn_dis1(&self) -> bool

Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.

pub fn set_rpdfn_dis1(&mut self, val: bool)

Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.

pub const fn dwnspread1(&self) -> Dwnspread

Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.

pub fn set_dwnspread1(&mut self, val: Dwnspread)

Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.

pub const fn inc_step(&self) -> u16

Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.

pub fn set_inc_step(&mut self, val: u16)

Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.

Trait Implementations

impl Clone for Pllsscgr

fn clone(&self) -> Pllsscgr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Pllsscgr

fn default() -> Pllsscgr

Returns the “default value” for a type.

impl PartialEq for Pllsscgr

fn eq(&self, other: &Pllsscgr) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Pllsscgr

impl Eq for Pllsscgr

impl StructuralEq for Pllsscgr

impl StructuralPartialEq for Pllsscgr