Struct Rcc

pub struct Rcc(pub *mut u8);

Reset and clock control

Tuple Fields

0: *mut u8

Implementations

impl Rcc

pub fn cr(self) -> Reg<Cr, RW>

RCC clock control register

pub fn icscr1(self) -> Reg<Icscr1, RW>

RCC internal clock sources calibration register 1

pub fn icscr2(self) -> Reg<Icscr2, RW>

RCC internal clock sources calibration register 2

pub fn icscr3(self) -> Reg<Icscr3, RW>

RCC internal clock sources calibration register 3

pub fn crrcr(self) -> Reg<Crrcr, RW>

RCC clock recovery RC register

pub fn cfgr1(self) -> Reg<Cfgr1, RW>

RCC clock configuration register 1

pub fn cfgr2(self) -> Reg<Cfgr2, RW>

RCC clock configuration register 2

pub fn cfgr3(self) -> Reg<Cfgr3, RW>

RCC clock configuration register 3

pub fn pll1cfgr(self) -> Reg<Pll1cfgr, RW>

RCC PLL1 configuration register

pub fn pll2cfgr(self) -> Reg<Pll2cfgr, RW>

RCC PLL2 configuration register

pub fn pll3cfgr(self) -> Reg<Pll3cfgr, RW>

RCC PLL3 configuration register

pub fn pll1divr(self) -> Reg<Pll1divr, RW>

RCC PLL1 dividers register

pub fn pll1fracr(self) -> Reg<Pll1fracr, RW>

RCC PLL1 fractional divider register

pub fn pll2divr(self) -> Reg<Pll2divr, RW>

RCC PLL2 dividers configuration register

pub fn pll2fracr(self) -> Reg<Pll2fracr, RW>

RCC PLL2 fractional divider register

pub fn pll3divr(self) -> Reg<Pll3divr, RW>

RCC PLL3 dividers configuration register

pub fn pll3fracr(self) -> Reg<Pll3fracr, RW>

RCC PLL3 fractional divider register

pub fn cier(self) -> Reg<Cier, RW>

RCC clock interrupt enable register

pub fn cifr(self) -> Reg<Cifr, RW>

RCC clock interrupt flag register

pub fn cicr(self) -> Reg<Cicr, RW>

RCC clock interrupt clear register

pub fn ahb1rstr(self) -> Reg<Ahb1rstr, RW>

RCC AHB1 peripheral reset register

pub fn ahb2rstr1(self) -> Reg<Ahb2rstr1, RW>

RCC AHB2 peripheral reset register 1

pub fn ahb2rstr2(self) -> Reg<Ahb2rstr2, RW>

RCC AHB2 peripheral reset register 2

pub fn ahb3rstr(self) -> Reg<Ahb3rstr, RW>

RCC AHB3 peripheral reset register

pub fn apb1rstr1(self) -> Reg<Apb1rstr1, RW>

RCC APB1 peripheral reset register 1

pub fn apb1rstr2(self) -> Reg<Apb1rstr2, RW>

RCC APB1 peripheral reset register 2

pub fn apb2rstr(self) -> Reg<Apb2rstr, RW>

RCC APB2 peripheral reset register

pub fn apb3rstr(self) -> Reg<Apb3rstr, RW>

RCC APB3 peripheral reset register

pub fn ahb1enr(self) -> Reg<Ahb1enr, RW>

RCC AHB1 peripheral clock enable register

pub fn ahb2enr1(self) -> Reg<Ahb2enr1, RW>

RCC AHB2 peripheral clock enable register 1

pub fn ahb2enr2(self) -> Reg<Ahb2enr2, RW>

RCC AHB2 peripheral clock enable register 2

pub fn ahb3enr(self) -> Reg<Ahb3enr, RW>

RCC AHB3 peripheral clock enable register

pub fn apb1enr1(self) -> Reg<Apb1enr1, RW>

RCC APB1 peripheral clock enable register 1

pub fn apb1enr2(self) -> Reg<Apb1enr2, RW>

RCC APB1 peripheral clock enable register 2

pub fn apb2enr(self) -> Reg<Apb2enr, RW>

RCC APB2 peripheral clock enable register

pub fn apb3enr(self) -> Reg<Apb3enr, RW>

RCC APB3 peripheral clock enable register

pub fn ahb1smenr(self) -> Reg<Ahb1smenr, RW>

RCC AHB1 peripheral clocks enable in Sleep and Stop modes register

pub fn ahb2smenr1(self) -> Reg<Ahb2smenr1, RW>

RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1

pub fn ahb2smenr2(self) -> Reg<Ahb2smenr2, RW>

RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2

pub fn ahb3smenr(self) -> Reg<Ahb3smenr, RW>

RCC AHB3 peripheral clocks enable in Sleep and Stop modes register

pub fn apb1smenr1(self) -> Reg<Apb1smenr1, RW>

RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1

pub fn apb1smenr2(self) -> Reg<Apb1smenr2, RW>

RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

pub fn apb2smenr(self) -> Reg<Apb2smenr, RW>

RCC APB2 peripheral clocks enable in Sleep and Stop modes register

pub fn apb3smenr(self) -> Reg<Apb3smenr, RW>

RCC APB3 peripheral clock enable in Sleep and Stop modes register

pub fn srdamr(self) -> Reg<Srdamr, RW>

RCC SmartRun domain peripheral autonomous mode register

pub fn ccipr1(self) -> Reg<Ccipr1, RW>

RCC peripherals independent clock configuration register 1

pub fn ccipr2(self) -> Reg<Ccipr2, RW>

RCC peripherals independent clock configuration register 2

pub fn ccipr3(self) -> Reg<Ccipr3, RW>

RCC peripherals independent clock configuration register 3

pub fn bdcr(self) -> Reg<Bdcr, RW>

RCC Backup domain control register

pub fn csr(self) -> Reg<Csr, RW>

RCC control/status register

pub fn seccfgr(self) -> Reg<Seccfgr, RW>

RCC secure configuration register

pub fn privcfgr(self) -> Reg<Privcfgr, RW>

RCC privilege configuration register

Trait Implementations

impl Clone for Rcc

fn clone(&self) -> Rcc

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Rcc

fn eq(&self, other: &Rcc) -> bool

Tests for self and other values to be equal, and is used by ==.

const fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Rcc

impl Eq for Rcc

impl Send for Rcc

impl StructuralPartialEq for Rcc

impl Sync for Rcc